1. Field of the Invention
The invention relates generally to the device configuration and manufacturing methods for fabricating the semiconductor power devices. More particularly, this invention relates to an improved and novel manufacturing process and device configuration for providing the MOSFET device with double epitaxial layers to improve the breakdown voltage while reducing the on-resistance of the semiconductor power device.
2. Description of the Related Art
In order to increase the switching speed of a semiconductor power device, it is desirable to reduce the electric charges between the gate and drain such that a reduction of a gate to drain capacitance Crss can be reduced. A thick oxide formed at the trench bottom of the trench gate is frequently implemented to reduce the gate to drain capacitance. However, a thicker oxide layer formed at the trench bottom may also cause further technical difficulties and limitations of device implementations. Since the epitaxial layer has a resistivity that is significantly dropped in order to satisfy a design target of further reducing the Rds, the device designers now confront another technical difficulty. With the reduction of the epitaxial resistivity, the device may not support the requirement that the breakdown voltage due to the fact that an early breakdown can occur at the trench bottom corners. A degradation of the breakdown voltage is therefore becoming a design and operation limitation.
Several patented inventions are implemented with thicker oxide layer in the bottom of the trenched gate in order to reduce the charges between the gate and the drain. FIG. 1A shows a trenched MOSFET device disclosed by Blanchard in U.S. Pat. No. 4,914,058. The trenched MOSFET device has a thicker gate oxide on the bottom and on the lower portion of the trench sidewalls. FIG. 1B shows a cross sectional view of another MOSFET device disclosed by U.S. Pat. Nos. 6,808,533, 6,833,584, and 6,720,616. The last trench on the right hand side is implemented as a field plate. However, as discussed above, when the resistivity of the epitaxial layer is decreased to provide a low Rds, the trench field plate may not support the breakdown voltage.
FIG. 1C is another cross sectional view of an alternate MOSFET device disclosed by U.S. Pat. No. 7,091,573 and Patent Publication 20070187753. A reduced Rds is achieved by reducing the epitaxial layer resistivity without degrading the breakdown voltage by applying a RESURF (Reduced Surface Electric Field) step oxide structure that has a reduced surface electric field with a thick oxide layer on the trench sidewall and the bottom surface of the trench. Additional disclosures of similar technologies are also published by M. A. Gajda et al “Industrialisation of Resurf Stepped Oxide Technology for power Transistors” (Proceedings of the 18th International Symposium on Power Semiconductor Device and ICs Jun. 4-8 2006 ISPD 2006) However, the trenched filed plate termination may not support the targeted breakdown voltage due to the lower epitaxial resistivity than the conventional devices. Furthermore, early breakdown can often occur at the trench bottom corners that limit the applications of the device.
Therefore, a need still exists in the art of power semiconductor device design and manufacture to provide new manufacturing method and device configuration in forming the semiconductor power devices such that the above discussed problems and limitations can be resolved.